All Implementation MessagesSun Jan 9 18:03:02 2011

Program All Implementation Messages - Errors, Warnings, and InfosNew
xstWARNING Xst:1780 - Signal <reg<11:10>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.New
xstWARNING Xst:1780 - Signal <reg<1:0>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.New
xstWARNING Xst:646 - Signal <dot_pipe<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.New
xstWARNING Xst:646 - Signal <dash_pipe<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.New
xstWARNING Xst:643 - "C:/Xilinx/Keyer3/Source/keyer.vhd" line 296: The result of a 32x3-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.New
xstWARNING Xst:2677 - Node <dot_pipe_0> of sequential type is unconnected in block <keyer>.New
xstWARNING Xst:2677 - Node <dot_pipe_1> of sequential type is unconnected in block <keyer>.New
xstWARNING Xst:2677 - Node <dash_pipe_0> of sequential type is unconnected in block <keyer>.New
xstWARNING Xst:2677 - Node <dash_pipe_1> of sequential type is unconnected in block <keyer>.New
xstWARNING Xst:2677 - Node <dot_pipe_0> of sequential type is unconnected in block <keyer>.New
xstWARNING Xst:2677 - Node <dot_pipe_1> of sequential type is unconnected in block <keyer>.New
xstWARNING Xst:2677 - Node <dash_pipe_0> of sequential type is unconnected in block <keyer>.New
xstWARNING Xst:2677 - Node <dash_pipe_1> of sequential type is unconnected in block <keyer>.New
xstWARNING Xst:1710 - FF/Latch <dot_time_31> (without init value) has a constant value of 0 in block <keyer>. This FF/Latch will be trimmed during the optimization process.New
xstWARNING Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dot_time_30> (without init value) has a constant value of 0 in block <keyer>. This FF/Latch will be trimmed during the optimization process.New
xstWARNING Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dot_time_29> (without init value) has a constant value of 0 in block <keyer>. This FF/Latch will be trimmed during the optimization process.New
xstWARNING Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dot_time_28> (without init value) has a constant value of 0 in block <keyer>. This FF/Latch will be trimmed during the optimization process.New
xstWARNING Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dot_time_27> (without init value) has a constant value of 0 in block <keyer>. This FF/Latch will be trimmed during the optimization process.New
xstWARNING Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dot_time_26> (without init value) has a constant value of 0 in block <keyer>. This FF/Latch will be trimmed during the optimization process.New
xstWARNING Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dot_time_25> (without init value) has a constant value of 0 in block <keyer>. This FF/Latch will be trimmed during the optimization process.New
xstWARNING Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dot_time_24> (without init value) has a constant value of 0 in block <keyer>. This FF/Latch will be trimmed during the optimization process.New
mapINFO MapLib:562 - No environment variables are currently set. 
mapINFO MapLib:159 - Net Timing constraints on signal clk are pushed forward through input buffer. 
mapINFO LIT:244 - All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. 
trceINFO Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. 
trceINFO Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. 
trceINFO Timing:3390 - This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation. 
trceINFO Timing:3389 - This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.